The invention relates to an integrated circuit containing a load capacitance. The invention also relates to an integrated reference source. In integrated circuits the delay of signal transitions has to lie within specified limits. This delay is partly caused by the internal delay in the signal-transferring gates. It is sometimes necessary to increase the delay of the gates artificially in order to meet the required specifications. It is generally known that signal transitions can be delayed by loading suitable nodal points in the gates with a load capacitance, which prevents rapid changes of voltage at the nodes. In the manufacture of integrated circuits it is necessary, however, to take account of process scatter, which may cause uncertainty in the prediction of internal delay values. At the same time the design of the circuit must be such that the signal transitions in a circuit manufactured under "worst-case" conditions as well as in the circuit manufactured uuder "best-case" conditions fall within the specified limits. This proves to be a particularly complicated problem in the design of an integrated circuit, since the delaying affect of a load capacitance increases with increasing internal delay in the gates (and with increasing internal output resistance, which determines the delay) so that the influence of the load capacitance depends to a very great extend on the unavoidable variations in the manufacturing process. Typical prior art circuits in this area are shown in U.S. Pat. Nos. 4,250,412 and 4,280,070, as well as European Pat. Nos. 23,798 and 47,128.